Espressif Systems /ESP32-C6 /EXTMEM /L1_CACHE_ACS_CNT_INT_CLR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as L1_CACHE_ACS_CNT_INT_CLR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (L1_IBUS0_OVF_INT_CLR)L1_IBUS0_OVF_INT_CLR 0 (L1_IBUS1_OVF_INT_CLR)L1_IBUS1_OVF_INT_CLR 0 (L1_IBUS2_OVF_INT_CLR)L1_IBUS2_OVF_INT_CLR 0 (L1_IBUS3_OVF_INT_CLR)L1_IBUS3_OVF_INT_CLR 0 (L1_BUS0_OVF_INT_CLR)L1_BUS0_OVF_INT_CLR 0 (L1_BUS1_OVF_INT_CLR)L1_BUS1_OVF_INT_CLR 0 (L1_DBUS2_OVF_INT_CLR)L1_DBUS2_OVF_INT_CLR 0 (L1_DBUS3_OVF_INT_CLR)L1_DBUS3_OVF_INT_CLR

Description

Cache Access Counter Interrupt clear register

Fields

L1_IBUS0_OVF_INT_CLR

The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due to bus0 accesses L1-ICache0.

L1_IBUS1_OVF_INT_CLR

The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due to bus1 accesses L1-ICache1.

L1_IBUS2_OVF_INT_CLR

Reserved

L1_IBUS3_OVF_INT_CLR

Reserved

L1_BUS0_OVF_INT_CLR

The bit is used to clear counters overflow interrupt and counters in L1-DCache due to bus0 accesses L1-DCache.

L1_BUS1_OVF_INT_CLR

The bit is used to clear counters overflow interrupt and counters in L1-DCache due to bus1 accesses L1-DCache.

L1_DBUS2_OVF_INT_CLR

Reserved

L1_DBUS3_OVF_INT_CLR

Reserved

Links

() ()